Design Summary: "CSRFile"
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Reviewer Name/ID:
Metrics for CSRFile Tasks
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
9 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
78.039MB |
01.919s |
02.326s |
02.326s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| --- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
92.637MB |
00.280s |
01.099s |
03.425s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
2 |
--- |
--- |
--- |
336.536um^2 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
2751 |
365 |
--- |
--- |
283 |
2910 |
--- |
--- |
118.047MB |
05.710s |
09.314s |
12.739s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
41 |
--- |
--- |
495 |
327.919um^2 |
836.192um^2 |
39.216% |
0 |
0.000mw |
0.000mw |
--- |
--- |
--- |
0 |
2794 |
365 |
28 |
313 |
283 |
2687 |
--- |
--- |
480.105MB |
09.050s |
10.395s |
23.135s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
42 |
0 |
--- |
495 |
359.820um^2 |
836.192um^2 |
43.031% |
0 |
0.000mw |
0.000mw |
--- |
0 |
0 |
0 |
2832 |
365 |
38 |
313 |
283 |
2725 |
--- |
--- |
1.954GB |
27.800s |
28.781s |
51.917s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
40 |
0 |
--- |
495 |
359.820um^2 |
836.192um^2 |
43.031% |
0 |
0.000mw |
0.000mw |
--- |
0 |
0 |
0 |
2832 |
365 |
38 |
313 |
283 |
2725 |
--- |
--- |
534.480MB |
13.990s |
15.391s |
01:07.308s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
0 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
574.156MB |
04.320s |
06.451s |
02:10.229s |