Design Summary: "CSRFile"

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Full CSRFile Metrics

- units import_verilog0 convert_verilog0 syn0 floorplan0 place0 cts0 route0 write_gds0 write_data0
errors 0 --- 0 0 0 0 0 0 0
warnings 9 --- 2 41 42 40 41 0 40
drvs --- --- --- --- 0 0 0 --- 0
drcs --- --- --- --- --- --- 0 --- ---
unconstrained --- --- --- 495 495 495 495 --- 495
cellarea um^2 --- --- 336.536 327.919 359.820 359.820 359.820 --- 359.820
totalarea um^2 --- --- --- 836.192 836.192 836.192 836.192 --- 836.192
utilization % --- --- --- 39.216 43.031 43.031 43.031 --- 43.031
logicdepth --- --- --- 0 0 0 0 --- 0
peakpower mw --- --- --- 0.000 0.000 0.000 0.000 --- 0.000
leakagepower mw --- --- --- 0.000 0.000 0.000 0.000 --- 0.000
irdrop mv --- --- --- --- --- --- --- --- 0.003
holdpaths --- --- --- --- 0 0 0 --- 0
setuppaths --- --- --- --- 0 0 0 --- 0
macros --- --- --- 0 0 0 0 --- 0
cells --- --- 2751 2794 2832 2832 2832 --- 2832
registers --- --- 365 365 365 365 365 --- 365
buffers --- --- --- 28 38 38 38 --- 38
inverters --- --- --- 313 313 313 313 --- 313
pins --- --- 283 283 283 283 283 --- 283
nets --- --- 2910 2687 2725 2725 2725 --- 2725
vias --- --- --- --- --- --- 27966 --- ---
wirelength um --- --- --- --- --- --- 10537.000 --- ---
memory B 78.039M 92.637M 118.047M 480.105M 1.954G 534.480M 3.944G 574.156M 645.461M
exetime s 01.919 00.280 05.710 09.050 27.800 13.990 55.100 04.320 53.770
tasktime s 02.326 01.099 09.314 10.395 28.781 15.391 56.113 06.451 54.851
totaltime s 02.326 03.425 12.739 23.135 51.917 01:07.308 02:03.422 02:10.229 02:58.629
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Metrics for CSRFile Tasks

Toggle import_verilog0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 9 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 78.039MB 01.919s 02.326s 02.326s
Toggle convert_verilog0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 92.637MB 00.280s 01.099s 03.425s
Toggle syn0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 2 --- --- --- 336.536um^2 --- --- --- --- --- --- --- --- --- 2751 365 --- --- 283 2910 --- --- 118.047MB 05.710s 09.314s 12.739s
Toggle floorplan0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 --- --- 495 327.919um^2 836.192um^2 39.216% 0 0.000mw 0.000mw --- --- --- 0 2794 365 28 313 283 2687 --- --- 480.105MB 09.050s 10.395s 23.135s
Toggle place0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 42 0 --- 495 359.820um^2 836.192um^2 43.031% 0 0.000mw 0.000mw --- 0 0 0 2832 365 38 313 283 2725 --- --- 1.954GB 27.800s 28.781s 51.917s
Toggle cts0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 0 --- 495 359.820um^2 836.192um^2 43.031% 0 0.000mw 0.000mw --- 0 0 0 2832 365 38 313 283 2725 --- --- 534.480MB 13.990s 15.391s 01:07.308s
Toggle route0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 0 0 495 359.820um^2 836.192um^2 43.031% 0 0.000mw 0.000mw --- 0 0 0 2832 365 38 313 283 2725 27966 10537.000um 3.944GB 55.100s 56.113s 02:03.422s
Toggle write_gds0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 574.156MB 04.320s 06.451s 02:10.229s
Toggle write_data0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 0 --- 495 359.820um^2 836.192um^2 43.031% 0 0.000mw 0.000mw 0.003mv 0 0 0 2832 365 38 313 283 2725 --- --- 645.461MB 53.770s 54.851s 02:58.629s
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